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Semiconductors

Chip-level link between digital certificates and physical authenticity

EPO Grants a Chip-Anchored NFT Patent for Physical Authentication

According to SEALSQ’s announcement of 18 June 2026, the European Patent Office has granted a divisional patent covering what the company calls a “Back-to-Physical” NFT architecture. The point is not an NFT in the abstract. The claimed model ties cryptographic credentials and ownership records to tamper-resistant semiconductor hardware so that a physical object carries a verifiable digital identity at chip level.That is why this development matters beyond blockchain headlines. For patent teams, the more interesting signal is that a data- and asset-heavy concept may become easier to defend...
South Korean fast-track patent review for advanced AI chip technologies

South Korea Expands Fast-Track Patent Review for Advanced AI Chips

South Korea’s Ministry of Intellectual Property (MOIP) announced on 10 September 2026 that it is broadening its Super Fast-Track examination framework for strategic technologies, extending coverage to areas including AI edge-computing chips, on-device large-model architectures and neuromorphic chips. Under MOIP’s current 2026 framework, eligible cases are targeted for a first examination result in about one month, making the route materially faster than ordinary examination and reinforcing the government’s push to secure rights around technologies with short product and investment...
A top view of a chip layout made of layered coloured circuit tracks, one region highlighted with a frame, with a document and a stamp beside it, symbolising the declaration and examination of original parts in IC layout-design registration

China's New Layout-Design Regime Takes Shape: CNIPA Issues New Implementing Rules, Transitional Measures and an Examination and Adjudication Guide

On 30 September the China National Intellectual Property Administration (CNIPA) released in one go three implementing documents for the new layout-design regime for integrated circuits: new Implementing Rules of the Regulations on the Protection of Layout Designs of Integrated Circuits (CNIPA Order No. 86), Transitional Measures on examination matters following the revised Regulations (Announcement No. 694) and a revised Guide to Examination and Administrative Adjudication of Layout Designs (Announcement No. 695). The Transitional Measures take effect on 15 October, the same day as the...
Weekly IP Brief issue 2610#2 cover: China's layout-design rules take effect as Madrid payments and EPO e-filing change

China's layout-design rules take effect as Madrid payments and EPO e-filing change

This issue covers the implementing rules for China's integrated circuit layout-design regime, the EPO's accelerated examination and full e-filing timetable, the switch in Madrid filing and WIPO payment channels, the evidence required to register AI-assisted works, and new cooperation between IP offices and online marketplaces against counterfeits.